HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 233

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Example 2: When an instruction that generates an exception branches using a branch instruction
Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs.
Instruction 2 ; May be executed if instruction 1 is a delay slot instruction and an instruction to store data to SQ.
Instruction 3
Instruction 4
Instruction 5
Instruction 6
Instruction 7 (branch destination of instruction 1)
Instruction 8 ; May be executed if an SQ store instruction.
Example 3: When an instruction that generates an exception does not branch using a branch instruction
Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs.
Instruction 2 ; May be executed if an SQ store instruction.
Instruction 3 ; May be executed if an SQ store instruction.
Instruction 4 ; May be executed if an SQ store instruction.
Instruction 5
To recover from this problem it is necessary that conditions A and B be satisfied.
A: After the PREF instruction to transfer data from the store queue (SQ0, SQ1) to external
B: There must be no PREF instruction to transfer data from the store queue to external memory
Notes: 1. If there are other instructions between the above two instructions, the problem can be
memory, a store instruction for the same store queue must be executed, and conditions (1) and
(2) below must be satisfied.
(1) Three NOP instructions *
(2) There must not be a PREF instruction to transfer data from the store queue to external
executed in the exception handling routine.
If such an instruction is executed, and if there is a store to the store queue instruction among
the four instructions *
memory by the PREF instruction may indicate that execution of the store instruction has
completed.
memory in the delay slot of the branch instruction.
avoided if the other instructions and NOP instructions together total three or more
instructions.
; May be executed if an SQ access instruction.
2
at the address referred to by SPC, the data transferred to external
1
must be inserted between the above two instructions.
Rev.7.00 Oct. 10, 2008 Page 147 of 1074
REJ09B0366-0700
Section 4 Caches