HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 17

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Item
9.7.2 Exit from
Hardware Standby
Mode
9.7.3 Usage Notes
9.8.1 In Reset
Figure 9.2 STATUS
Output in Manual Reset
9.8.5 Hardware
Standby Mode Timing
(SH7750S, SH7750R
Only)
Figure 9.15 Timing
When VDD-RTC Power
is Off → On
9.9 Usage Notes
Page
274
275
276
285
286
Revision (See Manual for Details)
Description amended
Setting the CA pin level high after the RESET pin level has
been set low and the SCK2 pin high starts the clock to oscillate.
The RESET pin level should be kept low until the clock has
stabilized, then set high so that the CPU starts the power-on
reset exiting procedure.
Description amended
1. The CA pin level must be kept high when the RTC power
2. On the SH7750R, power must be supplied to the other power
Figure amended
Note: * In a manual reset, STATUS = HH (reset) is set and an internal reset started after waiting
Figure amended
Note: * V
Newly added
V
STATUS
RESET *
DD
SCK2
CKIO
supply is started (figure 9.15).
supply pins (V
to the RTC power supply pin, in hardware standby mode.
V
, V
RESET
DD-RTC
SCK2
DDQ
until the end of the currently executing bus cycle.
CA
DD
Normal
*
, V
DD-PLL1/2
DD
, V
, V
≥ 0 Bcyc
DDQ
Must be asserted for
t
RESW
DDQ
Rev.7.00 Oct. 10, 2008 Page xv of lxxxiv
, V
, V
or longer
DD-CPG
DD
−
CPG
Min 0s
Power-on oscillation
setting time
, V
DD
Reset
−
PLL1
0–30 Bcyc
, and V
REJ09B0366-0700
DD
−
PLL2
Normal
), in addition