HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 628

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
Do not use DRAM/synchronous DRAM RAS down mode in partial-sharing master mode.
Area 2 synchronous DRAM mode register settings should be made by the master mode device. Set
partial-sharing master mode (by setting the PSHR bit to 1 in BCR1) after completion of the area 3
synchronous DRAM mode register settings.
In partial-sharing master mode, DMA transfer should not be performed on area 2, and the
DMAC's DDT mode should not be used.
13.3.15 Cooperation between Master and Slave
To enable system resources to be controlled in a harmonious fashion by master and slave, their
respective roles must be clearly defined. Before DRAM or synchronous DRAM is used,
initialization operations must be carried out. Responsibility must also be assigned when a standby
operation is performed to implement the power-down state.
The design of this LSI provides for all control, including initialization, refreshing, and standby
control, to be carried out by the master mode device. In a dual-processor configuration using direct
master/slave connection, all processing except direct access to memory is handled by the master.
In a combination of master mode and partial-sharing master mode, the partial-sharing master mode
processor performs initialization, refreshing, and standby control for the areas connected to it, with
the exception of area 2, while the master performs initialization of the memory connected to it.
If this LSI is specified as the master in a power-on reset, it will not accept bus requests from the
slave until the BREQ enable bit (BCR1.BREQEN) is set to 1.
To ensure that the slave processor does not access memory requiring initialization before use, such
as DRAM and synchronous DRAM, until initialization is completed, write 1 to the BREQ enable
bit after initialization ends.
Before setting self-refresh mode in standby mode, etc., write 0 to the BREQ enable bit to
invalidate the BREQ signal from the slave. Write 1 to the BREQ enable bit only after the master
has performed the necessary processing (refresh settings, etc.) for exiting self-refresh mode.
Rev.7.00 Oct. 10, 2008 Page 542 of 1074
REJ09B0366-0700