HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 259

MPU 3V 16K PB-FREE 208-QFP

HD6417750SF200V

Manufacturer Part Number
HD6417750SF200V
Description
MPU 3V 16K PB-FREE 208-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750SF200V

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 2.07 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750SF200V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(10) Slot Illegal Instruction Exception
• Sources:
• Transition address: VBR + H'0000 0100
• Transition operations:
Slot_illegal_instruction_exception()
{
}
⎯ Decoding of an undefined instruction in a delay slot
⎯ Decoding of an instruction that modifies PC in a delay slot
⎯ Decoding in user mode of a privileged instruction in a delay slot
⎯ Decoding of a PC-relative MOV instruction or MOVA instruction in a delay slot
The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and
R15 contents when this exception occurred are saved in SSR and SGR.
Exception code H'1A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100. Operation is not guaranteed if an undefined code other
than H'FFFD is decoded.
SPC = PC - 2;
SSR = SR;
SGR = R15;
EXPEVT = H'000001A0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Undefined instruction: H'FFFD
Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC
instructions that access GBR
Rev.7.00 Oct. 10, 2008 Page 173 of 1074
Section 5 Exceptions
REJ09B0366-0700

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