HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 793

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

In multiprocessor mode serial reception, the SCI operates as described below.
1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal
2. The received data is stored in SCRSR1 in LSB-to-MSB order.
3. If the MPIE bit is 1, MPIE is cleared to 0 when a 1 is received in the multiprocessor bit
4. If the MPIE bit is 0, RDRF is checked at the stop bit position, and if RDRF is 1 the overrun
15.3.4
In synchronous mode, data is transmitted or received in synchronization with clock pulses, making
it suitable for high-speed serial communication.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and the receiver also have a double-buffered structure, so
that data can be read or written during transmission or reception, enabling continuous data
transfer.
Figure 15.17 shows the general format for synchronous serial communication.
In synchronous serial communication, data on the transmission line is output from one falling edge
of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial
clock.
Note: * High except in continuous transmission/reception
Serial clock
Serial data
synchronization and starts reception.
position. If the multiprocessor bit is 0, the MPIE bit is not changed.
error bit is set. If the stop bit is not 0, the framing error bit is set. If RDRF is 0, the value in
SCRSR1 is transferred to SCRDR1, and if the stop bit is 0, RDRF is set to 1.
Operation in Synchronous Mode
Don't care
Figure 15.17 Data Format in Synchronous Communication
*
Bit 0
LSB
One unit of transfer data (character or frame)
Bit 1
Bit 2
Section 15 Serial Communication Interface (SCI)
Bit 3
Rev.7.00 Oct. 10, 2008 Page 707 of 1074
Bit 4
Bit 5
Bit 6
REJ09B0366-0700
MSB
Bit 7 Don't care
*