HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 830

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 0—Receive Data Ready (DR): Indicates that there are fewer than the receive trigger set
number of data bytes in SCFRDR2, and no further data has arrived for at least 15 etu after the stop
bit of the last data received.
Bit 0: DR
0
1
Note:
16.2.8
SCBRR2 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SCSMR2.
SCBRR2 can be read or written to by the CPU at all times.
SCBRR2 is initialized to H'FF by a power-on reset or manual reset. It is not initialized in standby
mode or in the module standby state.
Rev.7.00 Oct. 10, 2008 Page 744 of 1074
REJ09B0366-0700
Initial value:
*
Bit Rate Register (SCBRR2)
Equivalent to 1.5 frames with an 8-bit, 1-stop-bit format.
etu: Elementary time unit (time for transfer of 1 bit)
R/W:
Bit:
Description
Reception is in progress or has ended normally and there is no receive data
left in SCFRDR2
[Clearing conditions]
•
•
•
No further receive data has arrived
[Setting condition]
When SCFRDR2 contains fewer than the receive trigger set number of
receive data bytes, and no further data has arrived for at least 15 etu after
the stop bit of the last data received*
R/W
7
1
Power-on reset or manual reset
When all the receive data in SCFRDR2 has been read after reading DR
= 1, and 0 is written to DR
When all the receive data in SCFRDR2 has been read by the DMAC
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
(Initial value)
R/W
0
1