HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 384

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 10 Clock Oscillation Circuits
10.5
There are two methods of changing the internal clock frequency: by changing stopping and
starting of PLL circuit 1, and by changing the frequency division ratio of each clock. In both cases,
control is performed by software by means of the frequency control register. These methods are
described below.
10.5.1
When PLL circuit 1 is changed from the stopped to started state, a PLL stabilization time is
required. The oscillation stabilization time count is performed by the on-chip WDT.
1. Set a value in WDT to provide the specified oscillation stabilization time, and stop the WDT.
2. Set the PLL1EN bit to 1.
3. Internal processor operation stops temporarily, and the WDT starts counting up. The internal
4. After the WDT count overflows, clock supply begins within the chip and the processor
10.5.2
When PLL circuit 2 is on, a PLL circuit 1 and PLL circuit 2 oscillation stabilization time is
required.
1. Make WDT settings as in section 10.5.1.
2. Set the PLL1EN bit to 1.
3. Internal processor operation stops temporarily, PLL circuit 1 oscillates, and the WDT starts
4. After the WDT count overflows, PLL circuit 2 starts oscillating. The WDT resumes its up-
5. After the WDT count overflows, clock supply begins within the chip and the processor
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The following settings are necessary:
WTCSR register TME bit = 0: WDT stopped
WTCSR register CKS2–CKS0 bits: WDT count clock division ratio
WTCNT counter: Initial counter value
clock stops and an unstable clock is output to the CKIO pin.
resumes operation. The WDT stops after overflowing.
counting up. The internal clock stops and an unstable clock is output to the CKIO pin.
count from the value set in step 1 above. During this time, also, the internal clock is stopped
and an unstable clock is output to the CKIO pin.
resumes operation. The WDT stops after overflowing.
Changing the Frequency
Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off)
Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On)