HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 625

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
13.3.12 Master Mode
The master mode processor holds the bus itself unless it receives a bus request.
On receiving an assertion (low level) of the bus request signal (BREQ) from off-chip, the master
mode processor releases the bus and asserts (drives low) the bus use permission signal (BACK) as
soon as the currently executing bus cycle ends. If a bus release request due to a refresh request has
not been issued, on receiving the BREQ negation (high level) indicating that the slave has released
the bus, the processor negates (drives high) the BACK signal and resumes use of the bus.
If a bus request is issued due to a memory refresh request in the bus-released state, the processor
negates the bus use permission signal (BACK), and on receiving the BREQ negation indicating
that the slave has released the bus, resumes use of the bus.
When the bus is released, all bus interface related output signals and input/output signals go to the
high-impedance state, except for the synchronous DRAM interface CKE signal and bus arbitration
BACK signal, and DACK0 and DACK1 which control DMA transfers.
With DRAM, the bus is released after precharging is completed. With synchronous DRAM, also, a
precharge command is issued for the active bank and the bus is released after precharging is
completed.
The actual bus release sequence is as follows.
First, the bus use permission signal is asserted in synchronization with the rising edge of the clock.
The address bus and data bus go to the high-impedance state in synchronization with the next
rising edge of the clock after this BACK assertion. At the same time, the bus control signals (BS,
CSn, RAS1, RAS2, WEn, RD, RD/WR, RD2, RD/WR2, CE2A, and CE2B) go to the high-
impedance state. These bus control signals are negated no later than one cycle before going to
high-impedance. Bus request signal sampling is performed on the rising edge of the clock.
The sequence for re-acquiring the bus from the slave is as follows.
As soon as BREQ negation is detected on the rising edge of the clock, BACK is negated and bus
control signal driving is started. Driving of the address bus and data bus starts at the next rising
edge of an in-phase clock. The bus control signals are asserted and the bus cycle is actually
started, at the earliest, at the clock rising edge at which the address and data signals are driven.
In order to reacquire the bus and start execution of a refresh operation or bus access, the BREQ
signal must be negated for at least two cycles.
Rev.7.00 Oct. 10, 2008 Page 539 of 1074
REJ09B0366-0700