HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 811

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

16.1
This LSI is equipped with a single-channel serial communication interface with built-in FIFO
buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform asynchronous
serial communication.
Sixteen-stage FIFO registers are provided for both transmission and reception, enabling fast,
efficient, and continuous communication.
16.1.1
SCIF features are listed below.
• Asynchronous serial communication
• Full-duplex communication capability
• On-chip baud rate generator allows any bit rate to be selected.
Serial data communication is executed using an asynchronous system in which
synchronization is achieved character by character. Serial data communication can be carried
out with standard asynchronous communication chips such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
There is a choice of 8 serial data transfer formats.
⎯ Data length: 7 or 8 bits
⎯ Stop bit length: 1 or 2 bits
⎯ Parity: Even/odd/none
⎯ Receive error detection: Parity, framing, and overrun errors
⎯ Break detection: If the receive data following that in which a framing error occurred is also
The transmitter and receiver are independent units, enabling transmission and reception to be
performed simultaneously.
The transmitter and receiver both have a 16-stage FIFO buffer structure, enabling fast and
continuous serial data transmission and reception.
Section 16 Serial Communication Interface with FIFO
at the space “0” level, and there is a frame error, a break is detected. When a framing error
occurs, a break can also be detected by reading the RxD2 pin level directly from the serial
port register (SCSPTR2).
Overview
Features
Section 16 Serial Communication Interface with FIFO (SCIF)
(SCIF)
Rev.7.00 Oct. 10, 2008 Page 725 of 1074
REJ09B0366-0700