HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 443

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13.1
The functions of the bus state controller (BSC) include division of the external memory space, and
output of control signals in accordance with various types of memory and bus interface
specifications. The BSC functions allow DRAM, synchronous DRAM, SRAM, ROM, etc., to be
connected to this LSI, and also support the PCMCIA interface protocol, enabling system design to
be simplified and data transfers to be carried out at high speed by a compact system.
13.1.1
The BSC has the following features:
• External memory space is managed as 7 independent areas
• SRAM interface
• DRAM interface
⎯ Maximum 64 Mbytes for each of areas 0 to 6
⎯ Bus width of each area can be set in a register (except area 0, which uses an external pin
⎯ Wait state insertion by RDY pin
⎯ Wait state insertion can be controlled by program
⎯ Specification of types of memory connectable to each area
⎯ Output the control signals of memory to each area
⎯ Automatic wait cycle insertion to prevent data bus collisions in case of consecutive
⎯ Write strobe setup time and hold time periods can be inserted in a write cycle to enable
⎯ Wait state insertion can be controlled by program
⎯ Wait state insertion by RDY pin
⎯ Row address/column address multiplexing according to DRAM capacity
⎯ Burst operation (fast page mode, EDO mode)
⎯ CAS-before-RAS refresh and self-refresh
setting)
memory accesses to different areas, or a read access followed by a write access to the same
area
connection to low-speed memory
Connectable areas: 0 to 6
Settable bus widths: 64, 32, 16, 8
Overview
Features
Section 13 Bus State Controller (BSC)
Rev.7.00 Oct. 10, 2008 Page 357 of 1074
Section 13 Bus State Controller (BSC)
REJ09B0366-0700