HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 169

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3.3.3
Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical memory space in
the SH-4 to be mapped onto any external memory space in 1-, 4-, or 64-Kbyte, or 1-Mbyte, page
units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be
increased to a maximum of 256. This is called the virtual memory space. Mapping from virtual
memory space to 29-bit external memory space is carried out using the TLB. Only when area 7 in
external memory space is accessed using virtual memory space, addresses H'1C00 0000 to H'1FFF
FFFF of area 7 are not designated as a reserved area, but are equivalent to the P4 area control
register area in the physical memory space. Virtual memory space is illustrated in figure 3.6.
In the state of cache enabling, when the areas of P0, P3, and U0 are mapped onto a PCMCIA
interface area by means of the TLB, it is necessary either to specify 1 for the WT bit or to specify
256
Address translation not possible
Address translation not possible
Address translation not possible
Address translation possible
Address translation possible
Virtual Address Space
Privileged mode
Non-cacheable
Non-cacheable
Cacheable
Cacheable
Cacheable
P0 area
P1 area
P2 area
P4 area
P3 area
Figure 3.6 Virtual Address Space (MMUCR.AT = 1)
memory space
External
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
Section 3 Memory Management Unit (MMU)
Rev.7.00 Oct. 10, 2008 Page 83 of 1074
256
Address translation possible
Store queue area
Address error
Address error
User mode
Cacheable
U0 area
REJ09B0366-0700