HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 580

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
Connecting a 128-Mbit/256-Mbit Synchronous DRAM with 64-bit Bus Width (SH7750R
Only): It is possible to connect 128-Mbit or 256-Mbit synchronous DRAMs with 64-bit bus width
to the SH7750R. RAS down mode is also available using a 128 Mbytes of external memory space
in area 2 or 3. Either eight 128-Mbit (4 M × 8 bit × 4 bank) DRAMs or four 256-Mbit (4 M × 8 bit
× 4 bank) DRAMs can be connected. Figure 13.45 shows an example in which four 256-Mbit
DRAMs are connected.
Notes on Usage:
• BCR1.DRAMTP2−DRAMTP0 = 011: Sets areas 2 and 3 as synchronous-DRAM-interface
• MCR.SZ = 00: Sets the bus width of the synchronous DRAM to 64 bits.
• MCR.AMX = 6: Selects the 128-Mbit or 256-Mbit address-multiplex setting for the
• In the auto-refresh operation, the REF command is issued twice continuously in response to a
Rev.7.00 Oct. 10, 2008 Page 494 of 1074
REJ09B0366-0700
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D31–D0 (read)
BS
CKE
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
spaces.
synchronous DRAM.
single refresh request. The interval cycle number between the first and second REF commands
issuance is specified by the setting of the TRAS2–TRAS0 bits in MCR, which is 4 to 11 CKIO
Figure 13.44 Basic Timing of a Burst Write to Synchronous DRAM
Tr
Row
Row
Row
Trw
Tc1
c1
Tc2
c2
H/L
c1
Tc3
c3
Tc4
c4
Tc5
c5
Tc6
c6
H/L
c5
Tc7
c7
Tc8
c8
Trw1
Trw1
Tpc