HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 200

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Caches
4.2
There are three cache and store queue related control registers, as shown in figure 4.1.
(1) Cache Control Register (CCR): CCR contains the following bits:
EMODE: Double-sized cache mode (Only for SH7750R; reserved bit for SH7750 and SH7750S)
IIX:
ICI:
ICE:
OIX:
ORA:
OCI:
CB:
WT:
OCE:
Longword access to CCR can be performed from H'FF00 001C in the P4 area and H'1F00 001C in
area 7. The CCR bits are used for the cache settings described below. Consequently, CCR
modifications must only be made by a program in the non-cached P2 area. After CCR is updated,
Rev.7.00 Oct. 10, 2008 Page 114 of 1074
REJ09B0366-0700
CCR
QACR0
QACR1
Notes:
31 30
31
31
EMODE *
Register Descriptions
IC index enable
IC invalidation
IC enable
OC index enable
OC RAM enable
OC invalidation
Copy-back enable
Write-through enable
OC enable
* SH7750R only
indicates reserved bits: 0 must be specified in a write; the read value is 0.
Figure 4.1 Cache and Store Queue Control Registers
16 15
IIX
14
12 11 10 9 8 7 6 5 4 3 2
ICI ICE
OIX
ORA
5 4
5 4
AREA
AREA
OCI
CB
2 1 0
2 1 0
WT OCE
1 0