HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 232

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Caches
4.7.6
If an exception occurs within the three instructions preceding an instruction that writes to an SQ in
the SH7750 and SH7750S, a branch may be made to the exception handling routine after
execution of the SQ write that should be suppressed when an exception occurs.
This may be due to the bug described in (1) or (2) below.
(1) When SQ data is transferred to external memory within a normal program
(2) When SQ data is transferred to external memory in an exception handling routine
Example 1: When an SQ store instruction is executed after a PREF instruction for transfer from that same SQ
PREF instruction
Instruction 1 ; May be executed if an SQ store instruction.
Instruction 2 ; May be executed if an SQ store instruction.
Instruction 3 ; May be executed if an SQ store instruction.
Instruction 4 ; Not executed even if an SQ store instruction.
Rev.7.00 Oct. 10, 2008 Page 146 of 1074
REJ09B0366-0700
If a PREF instruction for transfer from an SQ to external memory is included in the three
instructions preceding an SQ store instruction, the SQ is updated because the SQ write that
should be suppressed when a branch is made to the exception handling routine is executed, and
after returning from the exception handling routine the execution order of the PREF instruction
and SQ store instruction is reversed, so that erroneous data may be transferred to external
memory.
If store queue contents are transferred to external memory within an exception handling
routine, erroneous data may be transferred to external memory.
; PREF instruction for transfer from SQ to external memory
; Address of this instruction is saved to SPC when exception occurs.
; Instruction 1, instruction 2, or instruction 3 may be executed on return from exception handling routine.
SQ Usage Notes
to external memory