UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 125

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Address
FFFDCH Priority specification flag register 12L PR12L
FFFDDH Priority specification flag register
FFFBAH DMA mode control register 0
FFFBBH DMA mode control register 1
FFFBCH DMA operation control register 0
FFFBDH DMA operation control register 1
FFFBEH Back ground event control register
Note
FFFB2H
FFFB3H
FFFB4H
FFFB5H
FFFB6H
FFFB7H
FFFB8H
FFFB9H
FFFC0H
FFFC2H
FFFC4H
FFFD0H Interrupt request flag register 2L
FFFD1H Interrupt request flag register 2H
FFFD4H Interrupt mask flag register 2L
FFFD5H Interrupt mask flag register 2H
FFFD8H Priority specification flag register 02L PR02L
FFFD9H Priority specification flag register
FFFE0H
FFFE1H
FFFE2H
FFFE3H
Do not directly operate this SFR, because it is to be used in the self programming library.
DMA RAM address register 0L
DMA RAM address register 0H
DMA RAM address register 1L
DMA RAM address register 1H
DMA byte count register 0L
DMA byte count register 0H
DMA byte count register 1L
DMA byte count register 1H
02H
12H
Interrupt request flag register 0L
Interrupt request flag register 0H
Interrupt request flag register 1L
Interrupt request flag register 1H
Special Function Register (SFR)
Name
−
−
−
DRA0L
DRA0H
DRA1L
DRA1H
DBC0L
DBC0H
DBC1L
DBC1H
DMC0
DMC1
DRC0
DRC1
BECTL
IF2L
IF2H
MK2L
MK2H
PR02H
PR12H
IF0L
IF0H
IF1L
IF1H
PFCMD
PFS
FLPMC
CHAPTER 3 CPU ARCHITECTURE
Symbol
Note
Table 3-5. SFR List (4/5)
User’s Manual U19678EJ1V1UD
Note
Note
DRA0
DRA1
DBC0
DBC1
IF2
MK2
PR02
PR12
IF0
IF1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
−
−
−
Manipulable Bit Range
1-bit
−
−
−
−
−
−
−
−
√
√
√
√
√
−
−
−
√
√
√
√
√
√
√
√
√
√
√
√
8-bit
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
√
√
√
√
√
√
√
√
√
√
√
√
16-bit
√
√
√
√
−
−
−
−
−
−
−
−
√
√
√
√
√
√
Undefined
Undefined
Undefined
Reset
After
FFH
FFH
FFH
FFH
FFH
FFH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
123
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√