UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 565
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UPD78F1211GB-GAF-AX
Manufacturer Part Number
UPD78F1211GB-GAF-AX
Description
MCU 16BIT 78K0R/LX3 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1211GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1211GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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10.2 Configuration of Watchdog Timer
option byte.
WDCS2 to WDCS0 of
option byte (000C0H)
WINDOW0 of option
WDTON of option
The watchdog timer includes the following hardware.
How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the
Remark f
WDTINT of option
WINDOW1 and
byte (000C0H)
byte (000C0H)
byte (000C0H)
f
IL
Remark For the option byte, see CHAPTER 23 OPTION BYTE.
Watchdog timer interval interrupt
Window open period
Controlling counter operation of watchdog timer
Overflow time of watchdog timer
Controlling counter operation of watchdog timer
(in HALT/STOP mode)
IL
: Internal low-speed oscillation clock frequency
Control register
controller
Clock
input
Setting of Watchdog Timer
(Count value overflow time
Item
Watchdog timer enable
Table 10-2. Setting of Option Bytes and Watchdog Timer
Window size check
register (WDTE)
Interval time controller
Figure 10-1. Block Diagram of Watchdog Timer
counter
Table 10-1. Configuration of Watchdog Timer
20-bit
Count clear
signal
CHAPTER 10 WATCHDOG TIMER
f
IL
Watchdog timer enable register (WDTE)
/2
7
User’s Manual U19678EJ1V1UD
to f
Internal bus
IL
/2
×
17
3/4)
decision signal
Selector
Window size
WDTE except ACH
Write detector to
Bit 7 (WDTINT)
Bits 6 and 5 (WINDOW1, WINDOW0)
Bit 4 (WDTON)
Bits 3 to 1 (WDCS2 to WDCS0)
Bit 0 (WDSTBYON)
Overflow signal
Configuration
Option Byte (000C0H)
controller
output
Reset
Interval time interrupt
Internal reset signal
563
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