UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 716
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1211GB-GAF-AX
Manufacturer Part Number
UPD78F1211GB-GAF-AX
Description
MCU 16BIT 78K0R/LX3 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1211GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1211GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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714
(Essential)
(Selective)
(Selective)
(Selective)
(Selective)
(Selective)
(Essential)
(Essential)
Changing setting of SPS0 register
Manipulating target for communication
Changing setting of SDR0n register
Changing setting of SCR0n register
Changing setting of SMR0n
Starting setting for resumption
Starting communication
Figure 13-82. Procedure for Resuming UART Reception
Writing to SS0
and SMR0r registers
Clearing error flag
CHAPTER 13 SERIAL ARRAY UNIT
register
User’s Manual U19678EJ1V1UD
Re-set the registers to change the serial
mode registers 0n, 0r (SMR0n, SMR0r)
setting.
Set the SS0n bit of the target channel to 1
and set SE0n bit to 1 (to enable operation).
Stop the target for communication or wait
until the target completes its operation.
Re-set the register to change the operation
clock setting.
Re-set the register to change the transfer
baud rate setting (setting the transfer clock
by dividing the operation clock (f
Re-set the register to change the serial
communication operation setting register
0n (SCR0n) setting.
If the FEF, PEF, and OVF flags remain
set, clear them using serial flag clear
The start bit is detected.
trigger register 0n (SIR0n).
MCK
)).
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