UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 775

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark
Note When bit 3 (TRC) of the IICA status register (IICS) is set to 1 (transmission status), bit 5
Condition for clearing (COI = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL = 1 (exit from communications)
• When IICE changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (TRC = 0)
<Both master and slave>
• When a stop condition is detected
• Cleared by LREL = 1 (exit from communications)
• When IICE changes from 1 to 0 (operation stop)
• Cleared by WREL = 1
• When ALD changes from 0 to 1 (arbitration loss)
• Reset
• When not used for communication (MSTS, EXC, COI
<Master>
• When “1” is output to the first byte’s LSB (transfer
<Slave>
• When a start condition is detected
• When “0” is input to the first byte’s LSB (transfer
direction specification bit)
= 0))
direction specification bit)
COI
TRC
0
1
0
1
(WREL) of IICCTL0 is set to 1 during the ninth clock and wait is canceled, after which TRC bit is
cleared (reception status) and the SDA0 line is set to high impedance. Release the wait
performed while TRC bit is 1 (transmission status) by writing to the IICA shift register.
LREL:
IICE:
Addresses do not match.
Addresses match.
Receive status (other than transmit status). The SDA0 line is set for high impedance.
Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at
the falling edge of the first byte’s ninth clock).
Figure 14-7. Format of IICA Status Register (IICS) (2/3)
Bit 6 of IICA control register 0 (IICCTL0)
Bit 7 of IICA control register 0 (IICCTL0)
Note
CHAPTER 14 SERIAL INTERFACE IICA
(wait cancel)
User’s Manual U19678EJ1V1UD
Detection of transmit/receive status
Detection of matching addresses
Condition for setting (COI = 1)
• When the received address matches the local
Condition for setting (TRC = 1)
<Master>
• When a start condition is generated
• When 0 (master transmission) is output to the LSB
<Slave>
• When 1 (slave transmission) is input to the LSB
address (slave address register (SVA))
(set at the rising edge of the eighth clock).
(transfer direction specification bit) of the first byte
(during address transfer)
(transfer direction specification bit) of the first byte
from the master (during address transfer)
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