UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 467

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark
TAUS
default
setting
Channel
default
setting
Operation
start
n = 01
m = 02 to 07
Sets the TAU0EN and TAUOPEN bits of the PER2
register to 1.
Sets the TPS0 register.
Sets the TMR00 and TMRn registers of each channel
to be used (determines operation mode of channels).
An interval (period) value is set to the TDR00 register of
the master channel, and the number of interrupts to be
thinned is set to the TDRn register of the slave channel
1.
[Real-time output trigger generation channel (slave 1)]
[Real-time output channel (slave 2 to 7)]
Sets the TOEn and TOEm bits to 1 and enables
output of TOn and TOm.
Clears the port register and port mode register to 0.
Sets the TOEn (slave 1) and TOEm (slave 2 to 7) bits
to 1 (only when operation is resumed).
The TS00 (master) and TSn (slave 1) bits of the TS0
register are set to 1 at the same time.
The TS00 and TSn bits automatically return to 0
because they are trigger bits.
Figure 7-71. Operation Procedure of Linked Real-Time Output Function (Type 2) (1/2)
Determines clock frequencies of CK00 and CK01.
Sets the TRCn bit to 1 (trigger generation channel).
Sets the TREn bit to 1 (real-time output enable).
Sets the TRCm bit to 0 (non-trigger generation
channel).
Sets the TREm bit to 1 (real-time output enable).
Software Operation
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TOn and TOm pins go into Hi-Z output state.
TOn and TOm do not change because channel has
stopped operating.
The TOn and TOm pins output the TOn and TOm set
levels.
TE00 = 1, TEn = 1
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
At the master channel, TCR00 loads the value of TDR00
by count clock input. INTTM00 is generated when the
MD000 bit of the TMR00 register is 1.
At the slave channel, TCRn loads the value of TDRn and
enters a state to wait for detection of INTTM00 of the
master channel.
Hardware Status
465