UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 932

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Low-voltage detection level select register (LVIS)
930
Address: FFFAAH
Symbol
Cautions 1. To stop LVI, be sure to clear (0) LVION by using a 1-bit memory manipulation instruction.
Note
Caution 1. Be sure to clear bits 4 to 7 to “0”.
This register selects the low-voltage detection level.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation input sets this register to 0EH.
LVIS
The reset value changes depending on the reset source.
If the LVIS register is reset by LVI, it is not reset but holds the current value. The value of this register is
reset to “0EH” if a reset other than by LVI is effected.
2. Input voltage from external input pin (EXLVI) must be EXLVI < V
3. When LVI is used in interrupt mode (LVIMD = 0) and LVISEL is set to 0, an interrupt request
4. To read LVIM after writing this register, secure the time of one or more clock.
LVIS3
0
0
0
0
0
0
0
0
1
1
7
0
signal (INTLVI) that disables LVI operation (clears LVION) when the supply voltage (V
less than or equal to the detection voltage (V
input pin (EXLVI) is less than or equal to the detection voltage (V
LVIIF may be set to 1.
Figure 21-3. Format of Low-Voltage Detection Level Select Register (LVIS)
After reset: 0EH
LVIS2
Other than above
0
0
0
0
1
1
1
1
0
0
6
0
Note
CHAPTER 21 LOW-VOLTAGE DETECTOR
LVIS1
0
0
1
1
0
0
1
1
0
0
5
0
R/W
User’s Manual U19678EJ1V1UD
LVIS0
4
0
0
1
0
1
0
1
0
1
0
1
V
V
V
V
V
V
V
V
V
V
Setting prohibited
LVI0
LVI1
LVI2
LVI3
LVI4
LVI5
LVI6
LVI7
LVI8
LVI9
LVIS3
3
(4.22 ±0.1 V)
(4.07 ±0.1 V)
(3.92 ±0.1 V)
(3.76 ±0.1 V)
(3.61 ±0.1 V)
(3.45 ±0.1 V)
(3.30 ±0.1 V)
(3.15 ±0.1 V)
(2.99 ±0.1 V)
(2.84 ±0.1 V)
LVI
) (if LVISEL = 1, input voltage of external
LVIS2
Detection level
2
LVIS1
DD
1
.
EXLVI
LVIS0
)) is generated and
0
DD
) is