UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 574

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

572
Cautions 1. Change the output clock after disabling clock output (PCLOEn = 0).
Remarks 1. 48-pin products of 78K0R/IC3, 78K0R/ID3: n = 0
Note
Address: FFFA5H (CKS0), FFFA6H (CKS1)
Symbol
CKSn
Setting an output clock exceeding 10 MHz is prohibited when 2.7 V ≤ V
2. To shift to STOP mode when the main system clock is selected (CSELn = 0), set PCLOEn = 0
2. f
3. f
PCLOEn
PCLOEn
before executing the STOP instruction. When the subsystem clock is selected (CSELn = 1),
PCLOEn = 1 can be set because the clock can be output in STOP mode.
78K0R/IE3 : n = 0, 1
MAIN
SUB
CSELn
<7>
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
: Subsystem clock frequency
: Main system clock frequency
Figure 11-2. Format of Clock Output Select Register n (CKSn)
CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
Output disable (default)
Output enable
CCSn2
6
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CCSn1
User’s Manual U19678EJ1V1UD
5
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
After reset: 00H
PCLBUZn output enable/disable specification
CCSn0
4
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R/W
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
CSELn
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
3
2
3
4
5
6
7
2
3
4
11
12
13
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
4.88 kHz
2.44 kHz
1.22 kHz
PCLBUZn output clock selection
10 MHz
f
MAIN
CCSn2
=
2
DD
.
Setting
prohibited
10 MHz
5 MHz
2.5 MHz
1.25 MHz
9.77 kHz
4.88 kHz
2.44 kHz
32.768 kHz
16.384 kHz
8.192 kHz
4.096 kHz
2.048 kHz
1.024 kHz
20 MHz
512 Hz
256 Hz
f
MAIN
CCSn1
1
=
Note
10 MHz
5 MHz
9.77 kHz
4.88 kHz
Setting
prohibited
Setting
prohibited
2.5 MHz
19.5 MHz
40 MHz
f
CCSn0
MAIN
0
=
Note
Note