UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 586
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1211GB-GAF-AX
Manufacturer Part Number
UPD78F1211GB-GAF-AX
Description
MCU 16BIT 78K0R/LX3 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1211GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1211GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(4) 10-bit A/D conversion result register (ADCR)
(5) 8-bit A/D conversion result register (ADCRH)
584
Symbol
ADCR
Caution When writing to A/D converter mode register (ADM), analog input channel specification register
Caution When writing to A/D converter mode register (ADM), analog input channel specification register
This register is a 16-bit register that stores the A/D conversion result in the select mode. The lower 6 bits are
fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation
register. The higher 8 bits of the conversion result are stored in FFF1FH and the lower 2 bits are stored in the
higher 2 bits of FFF1EH.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are
stored.
ADCRH can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: FFF1FH, FFF1EH
(ADS), and A/D port configuration register (ADPC), the contents of ADCR may become undefined.
Read the conversion result following conversion completion before writing to ADM, ADS, and
ADPC. Using timing other than the above may cause an incorrect conversion result to be read.
(ADS), and A/D port configuration register (ADPC), the contents of ADCRH may become
undefined. Read the conversion result following conversion completion before writing to ADM,
ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to
be read.
Address: FFF1FH
ADCRH
Symbol
Figure 12-8. Format of 8-bit A/D Conversion Result Register (ADCRH)
Figure 12-7. Format of 10-bit A/D Conversion Result Register (ADCR)
7
FFF1FH
After reset: 00H
After reset: 0000H
6
CHAPTER 12 A/D CONVERTER
User’s Manual U19678EJ1V1UD
5
R
4
R
3
2
0
FFF1EH
0
1
0
0
0
0
0
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