UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 335
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UPD78F1211GB-GAF-AX
Manufacturer Part Number
UPD78F1211GB-GAF-AX
Description
MCU 16BIT 78K0R/LX3 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1211GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1211GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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TOM0
TMRn
TOE0
TOL0
TO0
(a) Timer mode register n (TMRn)
(b) Timer output register 0 (TO0)
(c) Timer output enable register 0 (TOE0)
(d) Timer output level register 0 (TOL0)
(e) Timer output mode register 0 (TOM0)
Remark
TOEn
TOMn
CKSn
TOLn
Bit n
Bit n
Bit n
Bit n
TOn
1/0
15
0
0
0
0
Figure 6-50. Example of Set Contents of Registers to Measure Input Pulse Interval
Operation clock selection
n = 00 to 11 (78K0R/IB3: n = 02 to 07 and 09)
14
0: Selects CK00 (channels 0 to 7) or CK02 (channels 8 to 11) as operation clock of channel n.
1: Selects CK01 (channels 0 to 7) or CK03 (channels 8 to 11) as operation clock of channel n.
0
CCS1n
0: Outputs 0 from TOn.
0: Stops TOn output operation by counting operation.
0: Cleared to 0 when TOMn = 0 (master channel output mode).
0: Sets master channel output mode.
13
0
CCS0n
12
0
Count clock selection
TERn
MAS
11
00B: Selects operation clock
0
CHAPTER 6 TIMER ARRAY UNIT TAUS
Slave/master selection
STSn2
10
0: Independent channel operation function
0
User’s Manual U19678EJ1V1UD
STSn1
9
0
Capture trigger selection
STSn0
001B: Selects the TIn pin input valid edge.
8
1
CISn1
1/0
7
CISn0
1/0
6
Selection of TIn pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Operation mode of channel n
0010B: Capture mode
5
0
Setting of operation when counting is started
0: Does not generate INTTMn when
1: Generates INTTMn when counting is
MDn4
counting is started.
started.
4
0
MDn3
3
0
MDn2
2
1
MDn1
1
0
MDn0
1/0
0
333
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