UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 451

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remarks
TAUS
default
setting
Channel
default
setting
Operation
start
During
operation
Figure 7-59. Operation Procedure When A/D Conversion Trigger Output Function (Type 2) Is Used (1/2)
Sets the TAU0EN and TAUOPEN bits of the PER2
register to 1.
Sets the TPS0 register.
Sets the TMRn and TMRm registers of channels to be
used (determines operation mode of channels).
An interval (period) value is set to the TDRn register of
the master channel, and an interrupt width is set to the
TDRm register of the slave channel.
Sets the master channel.
Sets the TOn bit, and determines default levels of the
TOn bit.
Sets the TOEn bit to 1 and enables operation of TOn.
Clears the port register and port mode register to 0.
Sets the TOEn (master) bit to 1 (only when operation is
resumed).
Sets the TSn (master) and TSm (slave) bits of the TS0
register to 1 at the same time.
The set value of the TDRn (master) register must be
changed during an up status period.
The set value of the TDRm (slave) register can be
changed.
The TCRn and TCRm registers can always be read.
The TSRm (slave) register can always be read.
1.
2.
Determines clock frequencies of CK00 and CK01.
Sets the TOMn bit of the TOM0 register to 0 (master
channel output mode).
Sets the TDEn bit of the TDE0 register to 0 (dead time
control enable).
The TSn and TSm bits automatically return to 0
because they are trigger bits.
OPM = 0: n = 00, m = 08, 09
OPM = 1: n = 00, 04, m = 01, 05
OPM: Bit15 of TAU option mode register (OPMR)
Software Operation
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TOn pin goes into Hi-Z output states.
The TOn default setting level is output when the port mode
register is in output mode and the port register is 0.
TOn does not change because channel stop operating.
The TOn pin outputs the set level of TOn.
TEn = 1, TEm = 1
At the master channel, TCRn loads the value of TDRn and
counts down. When the count value reaches TCRn =
0000H, INTTMn is generated. At the same time, the value of
TDRn is loaded to TCRn, and the counter starts counting
down again.
At the slave channel, TCRm loads the value of TDRm, and
counting down and up are switched according to the
operation of the master channel. INTTMm is generated and
count operation is stopped upon detection of TCRm =
0001H. TCRm loads the value of TDRm again and count
operation is continued by the generation of INTTMn during
an up status of the master channel.
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
When the master and slave channels start counting and
the MDn0 bit of the TMRn register is 1, INTTMn is
generated.
Hardware Status
449