UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 530

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UPD78F1211GB-GAF-AX

Manufacturer Part Number
UPD78F1211GB-GAF-AX
Description
MCU 16BIT 78K0R/LX3 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet

Specifications of UPD78F1211GB-GAF-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1211GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Address: F0241H (C0CTL), F0242H (C1CTL) After reset: 00H R/W
Symbol
CnCTL
528
(3) Comparator n control register (CnCTL)
This register is used to control the operation of comparator n, enable or disable comparator output, reverse the
output, and set the noise elimination width.
CnCTL can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
(Note, Caution, and Remark are listed on the next page.)
CnDFS2
CnINV
CnOE
CnEN
CnEN
<7>
0
1
0
0
0
0
1
0
1
0
1
Other than the above
Stops operation
Enables operation
Enables input to the external pins on the positive and negative sides of comparator n
Disables output (output signal = fixed to low level)
Enables output
Forward
Reverse
CnDFS1
Figure 8-5. Format of Comparator n Control Register (CnCTL)
CHAPTER 8 COMPARATORS/PROGRAMMABLE GAIN AMPLIFIERS
6
0
0
0
1
1
0
CnDFS0
5
0
0
1
0
1
0
User’s Manual U19678EJ1V1UD
Noise filter unused
250 ns
500 ns
1
2
Setting prohibited
Enabling or disabling of comparator output
μ
μ
s
s
CnOE
4
Comparator operation control
Output reversal setting
Noise elimination width setting (f
CnINV
3
CnDFS2
2
CLK
CnDFS1
= 20 MHz)
1
Note
CnDFS0
0

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