AT91SAM7S128C-MU Atmel, AT91SAM7S128C-MU Datasheet - Page 109

• Manufacturer Part Number: AT91SAM7S128C-MU
• Description: IC MCU ARM7 128K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S128C-MU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Core: ARM7TDMI
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S128-MU; AT91SAM7S128-MU

19.2.3
19.2.4
6175K–ATARM–30-Aug-10
Write Operations
Flash Commands
The internal memory area reserved for the embedded Flash can also be written through a write-
only latch buffer. Write operations take into account only the 8 lowest address bits and thus wrap
around within the internal memory area address space and appear to be repeated 1024 times
within it.
Write operations can be prevented by programming the Memory Protection Unit of the product.
Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
Write operations are performed in the number of wait states equal to the number of wait states
for read operations + 1, except for FWS = 3 (see
The EFC offers a command set to manage programming the memory flash, locking and unlock-
ing lock sectors, consecutive programming and locking, and full Flash erasing.
Table 19-2.
To run one of these commands, the field FCMD of the MC_FCR register has to be written with
the command number. As soon as the MC_FCR register is written, the FRDY flag is automati-
cally cleared. Once the current command is achieved, then the FRDY flag is automatically set. If
an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Mem-
ory Controller is activated.
All the commands are protected by the same keyword, which has to be written in the eight high-
est bits of the MC_FCR register.
Writing MC_FCR with data that does not contain the correct key and/or with an invalid command
has no effect on the memory plane; however, the PROGE flag is set in the MC_FSR register.
This flag is automatically cleared by a read access to the MC_FSR register.
When the current command writes or erases a page in a locked region, the command has no
effect on the whole memory plane; however, the LOCKE flag is set in the MC_FSR register. This
flag is automatically cleared by a read access to the MC_FSR register.
Command
Write page
Set Lock Bit
Write Page and Lock
Clear Lock Bit
Erase all
Set General-purpose NVM Bit
Clear General-purpose NVM Bit
Set Security Bit
Set of Commands
AT91SAM7S Series Preliminary
“MC Flash Mode Register” on page
Value
0x0B
0x0D
0x01
0x02
0x03
0x04
0x08
0x0F
Mnemonic
WP
SLB
WPL
CLB
EA
SGPB
CGPB
SSB
116).
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