AT91SAM7S128C-MU Atmel, AT91SAM7S128C-MU Datasheet - Page 127

• Manufacturer Part Number: AT91SAM7S128C-MU
• Description: IC MCU ARM7 128K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S128C-MU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Core: ARM7TDMI
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S128-MU; AT91SAM7S128-MU

20.2.3
20.2.4
20.2.4.1
Figure 20-3. AT91SAM7S512/256/128/64/321/161Parallel Programming Timing, Write Sequence
6175K–ATARM–30-Aug-10
Entering Programming Mode
Programmer Handshaking
Write Handshaking
MODE[3:0]
DATA[15:0]
The following algorithm puts the device in Parallel Programming Mode:
Note:
An handshake is defined for read and write operations. When the device is ready to start a new
operation (RDY signal set), the programmer starts the handshake by clearing the NCMD signal.
The handshaking is achieved once NCMD signal is high and RDY is high.
For details on the write handshaking sequence, refer to
4.
NVALID
NCMD
• Apply GND, VDDIO, VDDCORE, VDDFLASH and VDDPLL.
• Apply XIN clock within T
• Wait for T
• Start a read or write handshaking.
NOE
RDY
1
After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an
external clock (> 32 kHz) is connected to XIN, then the device switches on the external clock.
Else, XIN input is not considered. A higher frequency on XIN speeds up the programmer
handshake.
POR_RESET
2
3
POR_RESET
AT91SAM7S Series Preliminary
if an external clock is available.
4
5
Figure
20-3,
Figure 20-4
and
Table 20-
127