AT91SAM7S128C-MU Atmel, AT91SAM7S128C-MU Datasheet - Page 631

IC MCU ARM7 128K FLASH 64-QFN

AT91SAM7S128C-MU

Manufacturer Part Number
AT91SAM7S128C-MU
Description
IC MCU ARM7 128K FLASH 64-QFN
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91SAM7S128C-MU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Core
ARM7TDMI
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
AT91SAM7S128-MU
AT91SAM7S128-MU

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7S128C-MU
Manufacturer:
ATMEL
Quantity:
670
40.7.10
40.7.10.1
40.7.10.2
40.7.10.3
40.7.10.4
6175K–ATARM–30-Aug-10
Two-wire Interface (TWI)
TWI: Clock Divider
TWI: Software Reset
TWI: Disabling Does not Operate Correctly
TWI: NACK Status Bit Lost
The value of CLDIV x 2
be less than or equal to 8191⋅
None.
when a software reset is performed during a frame and when TWCK is low, it is impossible to ini-
tiate a new transfer in READ or WRITE mode.
None.
Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with
the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register
(TWI_SR) are not reset.
The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts
must be disabled before disabling the TWI.
During a master frame, if TWI_SR is read between the Non Acknowledge condition detection
and the TXCOMP bit rising in the TWI_SR, the NACK bit is not set.
The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as
long as transmission is not completed.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
CKDIV
must be less than or equal to 8191, the value of CHDIV x 2
AT91SAM7S Series Preliminary
CKDIV
must
631

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