AT91SAM7S128C-MU Atmel, AT91SAM7S128C-MU Datasheet - Page 347

• Manufacturer Part Number: AT91SAM7S128C-MU
• Description: IC MCU ARM7 128K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S128C-MU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Core: ARM7TDMI
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S128-MU; AT91SAM7S128-MU

T
30.10.5
Name:
Access:
Reset Value: 0x00000000
TWI_CWGR is only used in Master mode.
• CLDIV: Clock Low Divider
The SCL low period is defined as follows:
• CHDIV: Clock High Divider
The SCL high period is defined as follows:
T
• CKDIV: Clock Divider
The CKDIV is used to increase both SCL high and low periods.
6175K–ATARM–30-Aug-10
low
high
=
=
31
23
15
(
–
7
(
(
CLDIV
(
CHDIV
TWI Clock Waveform Generator Register
TWI_CWGR
Read-write
×
×
2
CKDIV
2
CKDIV
30
22
14
–
6
)
+
)
+
4 )
4 )
×
×
T
MCK
T
MCK
29
21
13
–
5
28
20
12
–
4
CHDIV
CLDIV
AT91SAM7S Series Preliminary
27
19
11
–
3
26
18
10
–
2
CKDIV
25
17
–
9
1
24
16
–
8
0
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