AT91SAM7S128C-MU Atmel, AT91SAM7S128C-MU Datasheet - Page 297
AT91SAM7S128C-MU
Manufacturer Part Number
AT91SAM7S128C-MU
Description
IC MCU ARM7 128K FLASH 64-QFN
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S128C-MU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Core
ARM7TDMI
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT91SAM7S128-MU
AT91SAM7S128-MU
AT91SAM7S128-MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7S128C-MU
Manufacturer:
ATMEL
Quantity:
670
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29.6.5
29.6.5.1
Figure 29-10. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 29-11. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
6175K–ATARM–30-Aug-10
TWD
TWD
TWD
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
Three bytes internal address
Two bytes internal address
One byte internal address
S
S
S
S
S
S
Internal Address
7-bit Slave Addressing
DADR
DADR
DADR
DADR
DADR
DADR
W
W
W
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address
devices and 10-bit slave address devices.
When Addressing 7-bit slave devices, the internal address bytes are used to perform random
address (read or write) accesses to reach one or more data bytes, within a memory page loca-
tion in a serial memory, for example. When performing read operations with an internal address,
the TWI performs a write operation to set the internal address into the slave device, and then
switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is
sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See
29-11
The three internal address bytes are configurable through the Master Mode register
(TWI_MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to
0.
In the figures below the following abbreviations are used:
W
W
W
• S
• P
• W
• R
• A
• N
• DADR
• IADR
A
A
A
and
A
A
A
IADR(23:16)
IADR(15:8)
IADR(7:0)
Figure
IADR(23:16)
IADR(15:8)
Start
Stop
Write
Read
Acknowledge
Not Acknowledge
Device Address
Internal Address
IADR(7:0)
29-12.
A
A
A
IADR(15:8)
A
A
A
IADR(7:0)
S
DADR
IADR(15:8)
IADR(7:0)
DATA
AT91SAM7S Series Preliminary
A
A
R
IADR(7:0)
S
A
A
A
A
DADR
IADR(7:0)
P
DATA
DATA
A
R
S
A
A
A
N
DADR
DATA
P
DATA
P
DATA
Figure
R
N
29-10,
A
P
A
N
P
P
Figure
297
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