AT91SAM7S128C-MU Atmel, AT91SAM7S128C-MU Datasheet - Page 724

• Manufacturer Part Number: AT91SAM7S128C-MU
• Description: IC MCU ARM7 128K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S128C-MU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Core: ARM7TDMI
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S128-MU; AT91SAM7S128-MU

40.19.7.9
40.19.7.10
40.19.7.11
40.19.8
40.19.8.1
40.19.8.2
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AT91SAM7S Series Preliminary
Synchronous Serial Controller (SSC)
SPI: Software Reset and SPIEN Bit
SPI: CSAAT = 1 and Delay
SPI: Bad Serial Clock Generation on 2nd Chip Select
SSC: Periodic Transmission Limitations in Master Mode
SSC: Transmitter Limitations in Slave Mode
The SPI Command “software reset” does not reset the SPIEN config bit. Therefore rewriting an
SPI enable command does not set TX_READY, TX_EMPTY flags.
Send SPI disable command after a software reset.
If CSAAT = 1 for current access and there is no more TX request for a time greater
than DLYBCT + DLYBCS, then if an access is requested on another slave, the NPCS bus
switches from one CS to the one requested without DLYBCS. External Slaves may reach a con-
tention on SPI_MISO line for a short period.
Assert the Last Transfer Command (NPCS de-activation) for the last character of each slave.
Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0.
This occurs using SPI with the following conditions:
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not
sent.
None.
If TK is programmed as output and TF is programmed as input, it is impossible to emit data
when the start of edge (rising or falling) of synchro has a Start Delay equal to zero.
None.
• Master Mode
• CPOL = 1 and NCPHA = 0
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
• Transmitting with the slowest chip select and then with the fastest one, then an additional
serial clock frequency equals the system clock frequency) and the other transfers set with
SCBR are not equal to 1
pulse is generated on output SPCK during the second transfer.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6175K–ATARM–30-Aug-10