AT91SAM7S128C-MU Atmel, AT91SAM7S128C-MU Datasheet - Page 459

• Manufacturer Part Number: AT91SAM7S128C-MU
• Description: IC MCU ARM7 128K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S128C-MU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Core: ARM7TDMI
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S128-MU; AT91SAM7S128-MU

33.6
Table 33-4.
Notes:
6175K–ATARM–30-Aug-10
0x00 + channel * 0x40 + 0x0C
0x00 + channel * 0x40 + 0x1C
0x00 + channel * 0x40 + 0x2C
0x00 + channel * 0x40 + 0x00
0x00 + channel * 0x40 + 0x04
0x00 + channel * 0x40 + 0x08
0x00 + channel * 0x40 + 0x10
0x00 + channel * 0x40 + 0x14
0x00 + channel * 0x40 + 0x18
0x00 + channel * 0x40 + 0x20
0x00 + channel * 0x40 + 0x24
0x00 + channel * 0x40 + 0x28
Timer Counter (TC) User Interface
1. Channel index ranges from 0 to 2.
2. Read-only if WAVE = 0
Offset
Register Mapping
0xC0
0xC4
0xFC
(1)
Register
Channel Control Register
Channel Mode Register
Reserved
Reserved
Counter Value
Register A
Register B
Register C
Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Block Control Register
Block Mode Register
Reserved
AT91SAM7S Series Preliminary
TC_CMR
TC_CCR
TC_BCR
TC_BMR
TC_IDR
TC_IMR
TC_IER
TC_RC
TC_CV
TC_RA
TC_RB
TC_SR
Name
–
Read-write
Read-write
Read-write
Read-write
Read-write
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Access
–
(2)
(2)
Reset
–
0
0
0
0
0
0
–
–
0
–
0
–
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