PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 117

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 10-12: PORTE FUNCTIONS
TABLE 10-13: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
 2010 Microchip Technology Inc.
RE0/LCDBIAS1
RE1/LCDBIAS2
RE3/COM0
RE4/COM1
RE5/COM2
RE6/COM3
RE7/CCP2/
SEG31
Legend:
Note 1:
PORTE
LATE
TRISE
PORTG
TRISG
LCDCON
LCDSE3
Legend: Shaded cells are not used by PORTE.
Pin Name
Name
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
TRISE7
LCDEN
SPIOD
LATE7
RDPU
SE31
Bit 7
RE7
LCDBIAS1
LCDBIAS2
Function
CCP2
SEG31
COM0
COM1
COM2
COM3
RE0
RE1
RE3
RE4
RE5
RE6
RE7
(1)
CCP2OD CCP1OD
TRISE6
SLPEN
LATE6
REPU
SE30
Bit 6
RE6
Setting
TRIS
—
—
0
1
0
1
0
1
x
0
1
x
0
1
x
0
1
x
0
1
0
1
x
TRISE5
LATE5
WERR
RJPU
SE29
Bit 5
RE5
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
TRISG4
TRISE4
LATE4
Preliminary
SE28
Bit 4
RE4
RG4
—
LATE<0> data output.
PORTE<0> data input.
LCD module bias voltage input.
LATE<1> data output.
PORTE<1> data input.
LCD module bias voltage input.
LATE<3> data output.
PORTE<3> data input.
LCD Common 0 output; disables all other outputs.
LATE<4> data output.
PORTE<4> data input.
LCD Common 1 output; disables all other outputs.
LATE<5> data output.
PORTE<5> data input.
LCD Common 2 output; disables all other outputs.
LATE<6> data output.
PORTE<6> data input.
LCD Common 3 output; disables all other outputs.
LATE<7> data output.
PORTE<7> data input.
CCP2 Compare/PWM output; takes priority over port data.
CCP2 Capture input.
Segment 31 analog output for LCD; disables digital output.
PIC18F87J72 FAMILY
TRISG3
TRISE3
LATE3
SE27
Bit 3
RG3
RE3
CS1
TRISG2
SE26
Bit 2
RG2
CS0
—
—
—
Description
TRISG1
TRISE1
LMUX1
LATE1
SE25
Bit 1
RE1
RG1
TRISG0
TRISE0
LMUX0
LATE0
SE24
Bit 0
RG0
DS39979A-page 117
RE0
on page
Values
Reset
52
52
52
52
52
51
51