PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 68

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F87J72 FAMILY
TABLE 6-3:
DS39979A-page 68
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
LCDPS
LCDSE0
LCDCON
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATG
LATF
LATE
LATD
LATC
LATB
LATA
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
Legend:
Note 1:
File Name
2:
3:
4:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
Alternate names and definitions for these bits when the MSSP module is operating in I
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier” for details.
RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
EUSART Baud Rate Generator Low Byte
EUSART Receive Register
EUSART Transmit Register
EEPROM Control Register 2 (not a physical register)
TRISA7
LATA7
OSCFIP
OSCFIE
INTSRC
OSCFIF
TRISD7
TRISC7
LCDEN
TRISF7
TRISE7
TRISB7
SPIOD
LATD7
LATC7
CSRC
LATF7
LATE7
LATB7
RDPU
RA7
SPEN
U2OD
SE07
Bit 7
WFT
RE7
RD7
RC7
RB7
RF7
—
—
—
—
—
—
—
PIC18F87J72 FAMILY REGISTER FILE SUMMARY (CONTINUED)
(4)
(4)
(4)
TRISA6
PLLEN
CCP2OD
BIASMD
LATA6
TRISE6
TRISD6
TRISC6
TRISB6
SLPEN
TRISF6
LATF6
LATE6
LATD6
LATC6
LATB6
LCDIP
LCDIF
LCDIE
U1OD
RA6
REPU
SE06
CMIP
CMIF
CMIE
ADIP
ADIF
ADIE
Bit 6
RX9
RF6
RE6
RD6
RC6
RB6
TX9
—
(4)
(4)
(3)
(4)
CCP1OD
WPROG
TRISF5
TRISE5
TRISD5
TRISC5
TRISB5
TRISA5
RJPU
WERR
RC2IP
RC2IE
RC1IP
RC1IE
LATF5
LATE5
LATD5
LATC5
LATB5
LATA5
SREN
RC2IF
RC1IF
TXEN
LCDA
TUN5
SE05
Bit 5
RF5
RE5
RD5
RC5
RB5
RA5
—
—
—
—
(2)
TRISG4
TRISF4
TRISE4
TRISD4
TRISC4
TRISB4
TRISA4
LATG4
LATF4
LATE4
LATD4
LATC4
LATB4
LATA4
SYNC
CREN
TX2IP
TX2IF
TX2IE
TX1IP
TX1IF
TX1IE
FREE
TUN4
SE04
Bit 4
RG4
RD4
RC4
RF4
RE4
RB4
RA4
WA
—
—
—
—
Preliminary
WRERR
CTMUIP
CTMUIF
CTMUIE
TRISG3
TRISD3
TRISC3
SENDB
ADDEN
TRISF3
TRISE3
TRISB3
TRISA3
LATG3
LATD3
LATC3
BCLIP
BCLIE
SSPIP
SSPIF
SSPIE
LATF3
LATE3
LATB3
LATA3
BCLIF
TUN3
SE03
Bit 3
RG3
RD3
RC3
LP3
CS1
RF3
RE3
RB3
RA3
CCP2IP
CCP2IF
CCP2IE
TRISG2
TRISD2
TRISC2
TRISF2
TRISB2
TRISA2
WREN
LATG2
LATD2
LATC2
BRGH
LVDIP
LVDIE
LATF2
LATB2
LATA2
FERR
LVDIF
TUN2
SE02
Bit 2
CS0
RG2
RD2
RC2
RB2
RA2
LP2
RF2
—
—
—
—
—
—
2
C™ Slave mode. See Section 18.4.3.2 “Address
TMR3IP
TMR3IE
TMR2IP
TMR2IE
CCP1IP
CCP1IF
CCP1IE
TMR3IF
TMR2IF
TRISG1
TRISE1
TRISD1
TRISC1
TRISB1
TRISA1
LMUX1
TRISF1
LATG1
LATF1
LATE1
LATD1
LATC1
LATB1
TRMT
OERR
LATA1
TUN1
SE01
Bit 1
RG1
RF1
RE1
RD1
RC1
RB1
RA1
LP1
WR
 2010 Microchip Technology Inc.
RTCCIP
RTCCIF
RTCCIE
TMR1IP
TMR1IF
TMR1IE
TRISG0
TRISE0
TRISD0
TRISC0
TRISB0
TRISA0
LMUX0
LATG0
LATE0
LATD0
LATC0
LATB0
LATA0
TX9D
RX9D
TUN0
SE00
Bit 0
RG0
RE0
RD0
RC0
RB0
RA0
LP0
—
—
—
—
—
—
—
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000
0000 0000
000- 0000
---- ----
--00 x00-
-111 1111
-000 0000
-000 0000
11-- 111-
00-- 000-
00-- 000-
-111 1-11
-000 0-00
-000 0-00
0000 0000
0001 1111
1111 111-
1111 1-11
1111 1111
1111 1111
1111 1111
1111 1111
00-x xxxx
xxxx xxx-
xxxx x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
000x xxxx
xxxx xxx-
xxxx x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx0x 0000
POR, BOR
Value on
Details on
51, 243
51, 251
51, 249
51, 240
51, 241
51, 169
51, 170
51, 168
52, 102
52, 101
52, 100
52, 122
52, 120
52, 117
52, 115
52, 113
52, 110
52, 107
52, 122
52, 120
52, 117
52, 115
52, 113
52, 110
52, 107
52, 122
52, 120
52, 117
52, 115
52, 113
52, 110
52, 107
51, 78
51, 78
52, 96
52, 99
52, 95
52, 98
52, 94
52, 97
27, 52
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