PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 445

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

The gain of the transfer function of this filter is 1 at each
multiple of DMCLK (typically 1 MHz), so a proper
anti-aliasing filter must be placed at the inputs to
attenuate the frequency content around DMCLK and
keep the desired accuracy over the baseband of the
converter. This anti-aliasing filter can be a simple
first-order RC network with a sufficiently low time
constant to generate high rejection at DMCLK
frequency.
EQUATION B-13: SINC FILTER TRANSFER
The Normal-Mode Rejection Ratio (NMRR) or gain of
the transfer function is given by the following equation:
EQUATION B-14: MAGNITUDE OF
EQUATION B-15:
 2010 Microchip Technology Inc.
or,
where
where
NMRR f  
NMRR f  
H z  
DATA_CHn
DATA_CHn
z
=
sin
=
=
exp
c x  



FUNCTION H(z)
FREQUENCY RESPONSE
H(f)
-------------------------------- -
OSR 1 z
--------------------------------------------- -
sin
=
sin


1 z
--------------------- -
DMCLK
=
–
=
=
c
---------------------------- -
sin
c
sin

2fj





-------------- -
sin


–



c 
c 
OSR
–

------------------------------------- -

------------------------------------- -
V

V



CH


CH
x
--------------------- -
DMCLK
x  
REF+
--------------------
DRCLK
REF+
–
1




n+
n+

---- -
f
--- -
f



f
f
f
f
D
S
3




–
–
–
–
3
CH
V
CH
V




REF-
REF-
3
n-
n-








8,388,608 G
32 768
Preliminary
,

G 3


PIC18F87J72 FAMILY

Figure B-3 shows the sinc filter frequency response:
FIGURE B-3:
B.4.5
The second-order modulator, SINC
and analog input structure all work together to produce
the device transfer function for the analog to digital
conversion (see Equation B-15).
The channel data is either a 16-bit or 24-bit word,
presented in 23-bit or 15-bit plus sign, two’s
complement format and is MSB (left) justified.
The ADC data is two or three bytes wide depending on
the WIDTH bit of the associated channel. The 16-bit
mode includes a round to the closest 16-bit word
(instead of truncation) in order to improve the accuracy
of the ADC data.
In case of positive saturation (CHn+ – CHn- > V
the output is locked to 7FFFFF for 24-bit mode (7FFF
for 16-bit mode). In case of negative saturation
(CHn+ – CHn-  V
800000 for 24-bit mode (8000 for 16-bit mode).
Equation B-15 is only true for DC inputs. For AC inputs,
this transfer function needs to be multiplied by the
transfer function of the SINC
and Equation B-14).
3
-100
-120
-20
-40
-60
-80
20
0
1
ADC OUTPUT CODING
(For 24-bit Mode Or WIDTH = 1)
(For 16-bit Mode Or WIDTH = 0)
10
SINC FILTER RESPONSE
WITH MCLK = 4 MHZ,
OSR = 64, PRESCALE = 1
REF
Input Frequency (Hz)
100
/3), the output code is locked to
1000
3
filter (see Equation B-13
10000
DS39979A-page 445
3
filter, PGA, V
100000 1000000
REF
REF
/3),