PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 86

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F87J72 FAMILY
7.5.3
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.5.4
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
TABLE 7-2:
DS39979A-page 86
TBLPTRU
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT
INTCON
EECON2 EEPROM Control Register 2 (not a physical register)
EECON1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash program memory access.
Name
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE
Bit 7
—
—
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Bit 6
—
—
WPROG
bit 21
Bit 5
Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
INT0IE
FREE
Bit 4
Preliminary
WRERR
RBIE
Bit 3
7.6
See Section 26.6 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
Flash Program Operation During
Code Protection
TMR0IF
WREN
Bit 2
INT0IF
Bit 1
WR
 2010 Microchip Technology Inc.
RBIF
Bit 0
—
Values on
Reset
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