PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 37

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
FIGURE 4-1:
FIGURE 4-2:
 2010 Microchip Technology Inc.
Peripheral
Program
Counter
T1OSI
OSC1
Note 1: T
Clock
Clock
CPU Clock
CPU
PLL Clock
Peripheral
Program
Counter
Output
T1OSI
OSC1
Clock
Q1
OST
SCS<1:0> Bits Changed
Q2
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
= 1024 T
PC
Q3
Q4
OSC
Q1
; T
Q1
PLL
T
OST
1
= 2 ms (approx). These intervals are not shown to scale.
(1)
PC
Q2
2
Clock Transition
T
3
PLL (1)
Q3
OSTS bit Set
Preliminary
Q4
PC + 2
n-1
PIC18F87J72 FAMILY
Figure 4-2). When the clock switch is complete, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCS bits are not affected by the wake-up; the Timer1
oscillator continues to run.
Q1
1
n
Transition
2
Clock
n-1 n
Q2
PC + 2
Q3
Q2
Q4
Q3 Q4
Q1
Q1
PC + 4
Q2
Q2
PC + 4
DS39979A-page 37
Q3
Q3