PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 462

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F87J72 FAMILY
B.6.5
The Configuration registers contain settings for the
internal clock prescaler, the oversampling ratio, the
Channel 0 and Channel 1 width settings, the state of
the channel Resets and shutdowns, the dithering algo-
rithm control (for Idle tones suppression), and the
control bits for the external V
REGISTER B-5:
DS39979A-page 462
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-4
bit 3-2
bit 1-0
PRESCALE
R/W-0
<1>
CONFIGURATION REGISTERS
PRESCALE<1:0>: Internal Master Clock (AMCLK) Prescaler Value bits
11 = AMCLK = MCLK/8
10 = AMCLK = MCLK/4
01 = AMCLK = MCLK/2
00 = AMCLK = MCLK (default)
OSR<1:0>: Oversampling Ratio for Delta-Sigma A/D Conversion bits (all channels, DMCLK/DRCLK)
11 = 256
10 = 128
01 = 64 (default)
00 = 32
WIDTH<1:0>: ADC Channel Output Data Word Width bits
11 = 24-bit mode on both channels
10 = 24-bit mode on Channel 1, 16-bit mode on Channel 0
01 = 16-bit mode on Channel 1, 24-bit mode on Channel 0
00 = 16 bit mode on both channels (default)
Reserved: Maintain as ‘0’
PRESCALE
R/W-0
<0>
CONFIG1: CONFIGURATION REGISTER 1: (ADDRESS 0x0A)
REF
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
OSR<1>
and external CLK.
R/W-0
OSR<0>
R/W-1
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WIDTH<1>
R/W-0
WIDTH<0>
R/W-0
 2010 Microchip Technology Inc.
x = Bit is unknown
r-0
r
r-0
r
bit 0