PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 272

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F87J72 FAMILY
20.5.2
The operation of the Synchronous Master and Slave
modes is identical except in the case of Sleep or any
Idle mode, and bit SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep, or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG2 register; if the RC2IE enable bit is set, the
interrupt generated will wake the chip from low-power
mode. If the global interrupt is enabled, the program will
branch to the interrupt vector.
TABLE 20-9:
DS39979A-page 272
INTCON
PIR3
PIE3
IPR3
RCSTA2
RCREG2
TXSTA2
SPBRG2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Name
AUSART SYNCHRONOUS
SLAVE RECEPTION
AUSART Receive Register
AUSART Baud Rate Generator Register
GIE/GIEH PEIE/GIEL TMR0IE
SPEN
CSRC
Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
—
—
—
LCDIF
LCDIE
LCDIP
Bit 6
RX9
TX9
RC2IE
RC2IP
RC2IF
SREN
TXEN
Bit 5
Preliminary
INT0IE
CREN
TX2IF
TX2IE
TX2IP
SYNC
Bit 4
CTMUIF
CTMUIE
CTMUIP
ADDEN
To set up a Synchronous Slave Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
RBIE
Bit 3
—
Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
If interrupts are desired, set enable bit, RC2IE.
If 9-bit reception is desired, set bit, RX9.
To enable reception, set enable bit, CREN.
Flag bit, RC2IF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RC2IE, was set.
Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG2 register.
If any error occurred, clear the error by clearing
bit, CREN.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR0IF
CCP2IE
CCP2IP
CCP2IF
BRGH
FERR
Bit 2
CCP1IE
CCP1IP
CCP1IF
INT0IF
OERR
TRMT
 2010 Microchip Technology Inc.
Bit 1
RTCCIE
RTCCIP
RTCCIF
RX9D
TX9D
RBIF
Bit 0
on Page
Values
Reset
49
52
52
52
54
54
54
54