PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 465

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

INDEX
A
A/D
Absolute Maximum Ratings .............................................. 389
AC (Timing) Characteristics .............................................. 404
ACKSTAT ......................................................................... 229
ACKSTAT Status Flag ...................................................... 229
ADCAL Bit ......................................................................... 281
ADCON0 Register............................................................. 273
ADCON1 Register............................................................. 273
ADCON2 Register............................................................. 273
ADDFSR ........................................................................... 377
ADDLW ............................................................................. 340
Addressable Universal Synchronous Asynchronous
ADDULNK ......................................................................... 377
ADDWF ............................................................................. 340
ADDWFC .......................................................................... 341
ADRESH Register............................................................. 273
ADRESL Register ..................................................... 273, 276
AFE
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A/D Converter Interrupt, Configuring ........................ 277
Acquisition Requirements ......................................... 278
ADCAL Bit................................................................. 281
ADCON0 Register..................................................... 273
ADCON1 Register..................................................... 273
ADCON2 Register..................................................... 273
ADRESH Register............................................. 273, 276
ADRESL Register ..................................................... 273
Analog Port Pins, Configuring................................... 279
Associated Registers ................................................ 281
Configuring the Module............................................. 277
Conversion Clock (T
Conversion Status (GO/DONE Bit) ........................... 276
Conversions .............................................................. 280
Converter Calibration ................................................ 281
Converter Characteristics ......................................... 421
Operation in Power-Managed Modes ....................... 281
Overview ................................................................... 273
Selecting and Configuring Automatic
Special Event Trigger (CCP)..................................... 280
Use of the CCP2 Trigger........................................... 280
Load Conditions for Device Timing
Parameter Symbology .............................................. 404
Temperature and Voltage Specifications .................. 405
Timing Conditions ..................................................... 405
GO/DONE Bit............................................................ 276
Receiver Transmitter (AUSART). See AUSART.
Analog Inputs ............................................................ 284
Block Diagram........................................................... 435
Boost Mode............................................................... 444
Data Ready Pin (DR) ................................................ 454
Delta-Sigma ADC Architecture ................................. 284
Delta-Sigma Modulator ............................................. 444
Electrical Characteristics................................... 423–425
External Voltage Reference ...................................... 447
Internal Clock Chain.................................................. 449
Internal Registers...................................................... 456
Internal Voltage Reference ............................... 284, 447
Output Coding........................................................... 445
Output Data Rates (table) ......................................... 439
Phase Delay Block............................................ 284, 448
Acquisition Time ............................................... 279
Specifications.................................................... 405
Block Diagram .................................................. 444
AD
) ............................................ 279
Preliminary
PIC18F87J72 FAMILY
Analog-to-Digital Converter. See A/D.
ANDLW............................................................................. 341
ANDWF............................................................................. 342
Assembler
AUSART
B
Baud Rate Generator ....................................................... 225
BC..................................................................................... 342
BCF .................................................................................. 343
BF ..................................................................................... 229
BF Status Flag .................................................................. 229
Bias Generation (LCD)
Block Diagrams
Power-On Reset ....................................................... 447
Programmable Gain Amplifiers................................. 284
Register Map .................................................... 285, 456
Registers
Required Connections .............................................. 287
Resolution................................................................. 446
Serial Interface ................................................. 286, 449
Serial Interface Characteristics................................. 426
SINC
Terminology...................................................... 438–443
Using ........................................................................ 288
Voltage Reference.................................................... 447
MPASM Assembler .................................................. 386
Asynchronous Mode................................................. 264
Baud Rate Generator (BRG) .................................... 262
Synchronous Master Mode....................................... 268
Synchronous Slave Mode......................................... 271
Charge Pump Design Considerations ...................... 177
A/D............................................................................ 276
AFE, Required Connections ..................................... 287
Analog Input Model................................................... 277
AUSART Receive ..................................................... 266
AUSART Transmit .................................................... 264
CONFIG1.......................................................... 462
CONFIG2.......................................................... 463
DATA_CHn....................................................... 457
GAIN................................................................. 459
PHASE ............................................................. 458
STATUS/COM .................................................. 461
Continuous Communication ............................. 452
Associated Registers, Receive......................... 267
Associated Registers, Transmit........................ 265
Receiver ........................................................... 266
Setting up 9-Bit Mode with
Transmitter ....................................................... 264
Associated Registers........................................ 262
Baud Rate Error, Calculating............................ 262
Baud Rates, Asynchronous Modes .................. 263
High Baud Rate Select (BRGH Bit) .................. 262
Operation in Power-Managed Modes............... 262
Sampling .......................................................... 262
Associated Registers, Receive......................... 270
Associated Registers, Transmit........................ 269
Reception ......................................................... 270
Transmission .................................................... 268
Associated Registers, Receive......................... 272
Associated Registers, Transmit........................ 271
Reception ......................................................... 272
Transmission .................................................... 271
3
Filter ...................................................... 284, 444
Address Detect......................................... 266
DS39979A-page 465