PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 122

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F87J72 FAMILY
TABLE 10-16: PORTG FUNCTIONS
TABLE 10-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
DS39979A-page 122
RG0/LCDBIAS0
RG1/TX2/CK2
RG2/RX2/DT2/
V
RG3/V
RG4/SEG26/
RTCC
Legend:
PORTG
LATG
TRISG
LCDSE3
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
LCAP
Pin Name
Name
1
LCAP
2
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
LCDBIAS0
Function
SPIOD
V
V
SEG26
RDPU
U2OD
SE31
RTCC
Bit 7
RG0
RG1
RG2
RG3
RG4
TX2
CK2
RX2
DT2
LCAP
LCAP
1
2
CCP2OD CCP1OD TRISG4
Setting
REPU
U1OD
SE30
TRIS
Bit 6
0
1
x
0
1
1
1
1
0
1
1
1
1
x
0
1
x
0
1
x
x
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
RJPU
SE29
Bit 5
—
Type
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
Preliminary
LATG4
SE28
Bit 4
RG4
LATG<0> data output.
PORTG<0> data input.
LCD module bias voltage input.
LATG<1> data output.
PORTG<1> data input.
Synchronous serial data output (AUSART module); takes priority over
port data.
Synchronous serial data input (AUSART module); user must configure
as an input.
Synchronous serial clock input (AUSART module).
LATG<2> data output.
PORTG<2> data input.
Asynchronous serial receive data input (AUSART module).
Synchronous serial data output (AUSART module); takes priority over
port data.
Synchronous serial data input (AUSART module); user must configure
as an input.
LCD charge pump capacitor input.
LATG<3> data output.
PORTG<3> data input.
LCD charge pump capacitor input.
LATG<4> data output.
PORTG<4> data input.
LCD Segment 26 output; disables all other pin functions.
RTCC output.
TRISG3
LATG3
SE27
Bit 3
RG3
TRISG2
LATG2
SE26
Bit 2
RG2
Description
TRISG1
LATG1
SE25
Bit 1
RG1
 2010 Microchip Technology Inc.
TRISG0
LATG0
SE24
Bit 0
RG0
Values on
Reset
page
52
52
52
51