PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 99

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER 9-9:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
—
Unimplemented: Read as ‘0’
LCDIE: LCD Interrupt Enable bit (valid when Type-B waveform with Non-Static mode is selected)
1 = Enabled
0 = Disabled
RC2IE: AUSART Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
TX2IE: AUSART Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
CTMUIE: CTMU Interrupt Enable bit
1 = Enabled
0 = Disabled
CCP2IE: CCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
RTCCIE: RTCC Interrupt Enable bit
1 = Enabled
0 = Disabled
LCDIE
R/W-0
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
W = Writable bit
‘1’ = Bit is set
RC2IE
R-0
TX2IE
R-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F87J72 FAMILY
CTMUIE
R/W-0
CCP2IE
R/W-0
x = Bit is unknown
CCP1IE
R/W-0
DS39979A-page 99
RTCCIE
R/W-0
bit 0