IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 10

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

1–4
Resource Utilization
System Requirements
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
f
This section lists resource utilization for the QDR II and QDR II+ SRAM controllers
with UniPHY for supported device families. Resource utilizations are derived with all
parameters at their default values.
Table 1–4
in the Quartus II software version 10.1 for Arria II GZ, Stratix III, Stratix IV, and
Stratix V devices.
Table 1–4. Resource Utilization in Arria II GZ, Stratix III, Stratix IV, and Stratix V
Devices
The RLDRAM II controller with UniPHY is part of the MegaCore IP Library, which is
distributed with the Quartus II software.
For system requirements and installation instructions, refer to
Installation &
Note to
(1) Half-rate designs use the same amount of memory as full-rate designs, but the data is organized in a different way
Rate
PHY
Half
Full
(half the width, double the depth) and the design may need more M9K resources.
Table
(Note 1)
shows the typical resource usage of the RLDRAM II controller with UniPHY
1–4:
Licensing.
Memory
Width
(Bits)
18
36
18
36
9
9
Combinational
ALUTS
1145
1713
1182
1678
829
892
Logic Registers
1147
1861
1197
1874
763
839
December 2010 Altera Corporation
Altera Software
Memory
(Bits)
1152
1152
Chapter 1: About This IP
288
576
288
576
Resource Utilization
Blocks
M9K
1
2
4
1
1
2