IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 33

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
Board Settings
December 2010 Altera Corporation
Intersymbol Interference
Table 3–7. Setup and Hold Derating Parameters (Part 2 of 2)
Intersymbol interference (ISI), occurs when a signal is distorted due to the
interference of one symbol with subsequent symbols. Typically, ISI is greater at
device depths greater than one because there are multiple stubs causing reflections.
The advanced I/O timing analysis capabilities of the Quartus II software already
includes ISI effects for device depth of one.
Table 3–8
Table 3–8. Intersymbol Interference Settings
tDH CK/CK# Crossing to VIH MIN
Derated tAS
Derated tAH
Derated tDS
Derated tDH
Address/command eye reduction
(setup)
Address/command eye reduction
(hold)
DQ eye reduction
Delta K arrival time
describes the intersymbol interference settings.
Parameters
Parameter
For a given data and DK/DK# slew rate, the memory device
data sheet provides a corresponding "tDH CK/CK# Crossing
to VIH MIN" value that can be used to determine the derated
data hold time.
The derated address/command setup time is calculated
automatically from the "tAS", the "tAS Vref to CK/CK#
Crossing", and the "tAS VIH MIN to CK/CK# Crossing"
parameters.
The derated address/command hold time is calculated
automatically from the "tAH", the "tAH CK/CK# Crossing to
Vref", and the "tAH CK/CK# Crossing to VIH MIN"
parameters.
The derated data setup time is calculated automatically
from the "tDS", the "tDS Vref to CK/CK# Crossing", and the
"tDS VIH MIN to CK/CK# Crossing" parameters.
The derated data hold time is calculated automatically from
the "tDH", the "tDH CK/CK# Crossing to Vref", and the "tDH
CK/CK# Crossing to VIH MIN" parameters.
The reduction in the eye diagram on the setup side (or left
side of the eye) due to ISI on the address/command signals
compared to a case where there is no ISI.
The reduction in the eye diagram on the hold side (or right
side of the eye) due to ISI on the address/command signals
compared to a case where there is no ISI.
The total reduction in the eye diagram due to ISI on DQ
signals compared to a case where there is no ISI. (It is
assumed that the ISI reduces the eye width symmetrically
on the left and right sides of the eye.)
The increase in variation on the range of arrival times of
DQS compared to a case when there is no ISI. (It is
assumed that the ISI causes DQS to further vary
symmetrically to the left and right.)
Section IV. RLDRAM II Controller with UniPHY IP User Guide
External Memory Interface Handbook Volume 3
Description
Description
3–5