IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 57

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—UniPHY
PHY-to-Controller Interfaces
Figure 6–10. Full-Rate Reads
December 2010 Altera Corporation
afi_rdata_valid
afi_rdata_en
mem_dqs
mem_dq
afi_rdata
afi_cs_n
afi_addr
clock
Figure 6–9
Figure 6–9. Full-Rate Write
After calibration completes, the sequencer sends the write latency in number of clock
cycles to the controller.
Figure 6–10
afi_wdata_valid
afi_dqs_burst
1
afi_wdata
afi_clk
shows a full-rate write.
shows full-rate reads;
2
3
--
4
afi_rlat = 9
Figure 6–11
5
a
6
Section IV. RLDRAM II Controller with UniPHY IP User Guide
shows half-rate reads.
b
7
External Memory Interface Handbook Volume 3
8
--
9
6–17