IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 13

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
MegaWizard Plug-In Manager Flow
December 2010 Altera Corporation
Specifying Parameters
The Qsys flow offers the following additional advantages over SOPC Builder:
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The MegaWizard Plug-In Manager flow allows you to customize your IP core and
manually integrate the function into your design.
To specify IP core parameters with the MegaWizard Plug-In Manager, follow these
steps:
1. Create a Quartus II project using the New Project Wizard available from the File
2. In the Quartus II software, launch the MegaWizard Plug-in Manager from the
3. To select a specific Altera IP core, click the IP core in the Installed Plug-Ins list in
4. Specify the parameters on the Parameter Settings pages. For detailed explanations
5. If the IP core provides a simulation model, specify appropriate options in the
Provides visualization of hierarchical designs
Allows greater performance through interconnect elements and pipelining
Provides closer integration with the Quartus II software
menu.
Tools menu, and follow the prompts in the MegaWizard Plug-In Manager
interface to create or edit a custom IP core variation.
the MegaWizard Plug-In Manager.
of these parameters, refer to the “Parameter Settings” chapter in this document.
1
wizard to generate a simulation model.
1
f
c
Some IP cores provide preset parameters for specific applications. If you
wish to use preset parameters, click the arrow to expand the Presets list,
select the desired preset, and then click Apply. To modify preset settings, in
a text editor edit the <installation directory>\ip\altera\uniphy\lib\<IP
core>.qprs file.
Altera IP supports a variety of simulation models, including
simulation-specific IP functional simulation models and encrypted RTL
models, and plain text RTL models. These are all cycle-accurate models. The
models allow for fast functional simulation of your IP core instance using
industry-standard VHDL or Verilog HDL simulators. For some cores, only
the plain text RTL model is generated, and you can simulate that model.
For more information about functional simulation models for Altera IP
cores, refer to
Handbook.
Use the simulation models only for simulation and not for synthesis or any
other purposes. Using these models for synthesis creates a nonfunctional
design.
Simulating Altera Designs
Section IV. RLDRAM II Controller with UniPHY IP User Guide
in volume 3 of the Quartus II
External Memory Interface Handbook Volume 3
2–3