IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 58

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–18
Figure 6–11. Half-Rate Reads
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
afi_rdata_valid
afi_rdata_en
mem_dqs
mem_dq
afi_rdata
afi_cs_n
afi_addr
clock
10
AX
Figure 6–12
read from the same address. In each example, afi_rdata and afi_wdata align with
controller clock (afi_clk) cycles. All the data in the bit vector is valid at once.
The AFI has the following conventions:
■
■
Figure 6–12
■
■
■
With the AFI, high and low signals are combined in one signal, so for a single
chip-select (afi_cs_n) interface, afi_cs_n[1:0], where location 0 appears on the
memory bus on one mem_clk cycle and location 1 on the next mem_clk cycle.
1
Spaced reads and writes have the following definitions:
■
■
The burst length is four.
An 9-bit interface with one chip-select.
The data for one controller clock (afi_clk) cycle represents data for two memory
clock (mem_clk) cycles (half-rate interface).
10
01
XA
Spaced writes—write commands separated by a gap of one controller clock
(afi_clk) cycle.
Spaced reads—read commands separated by a gap of one controller clock
(afi_clk) cycle.
This convention applies for all signals, so for an 9-bit memory interface, the
write data (afi_wdata) signal is afi_wdata[31:0], where the first data on
the DQ pins is afi_wdata[7:0], then afi_wdata[15:8], then
afi_wdata[23:16], then afi_wdata[31:24].
and
through
1
Figure 6–13
2
Figure 6–13
3
show writes and reads, where the data is written to and
assume the following general points:
4
afi_rlat = 9
5
6
Chapter 6: Functional Description—UniPHY
7
December 2010 Altera Corporation
8
10
DX
PHY-to-Controller Interfaces
9
01
XD