IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 51

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—UniPHY
UniPHY Signals
Table 6–5. AFI Signals
December 2010 Altera Corporation
Clocks and Reset
afi_clk
afi_reset_n
Address and Command
afi_addr
afi_ba
afi_cas_n
afi_cs_n
afi_ras_n
afi_we_n
Write Data
afi_dm
afi_wdata
afi_wdata_valid
Read Data
afi_rdata
afi_rdata_en
afi_rdata_valid
Calibration Control and Status
afi_cal_success
afi_cal_fail
Name
Table 6–5
shows the AFI signals.
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Output
Output
Output
Direction
1
1
MEM_ADDRESS_WIDTH ×
AFI_RATIO
MEM_BANK_WIDTH ×
AFI_RATIO
MEM_CONTROL_WIDTH ×
AFI_RATIO
MEM_CHIP_SELECT_
WIDTH × AFI_RATIO
MEM_CONTROL_WIDTH ×
AFI_RATIO
MEM_CONTROL_WIDTH ×
AFI_RATIO
MEM_DM_WIDTH ×
AFI_RATIO
MEM_DQ_WIDTH × 2 ×
AFI_RATIO
MEM_WRITE_DQS_
WIDTH × AFI_RATIO
MEM_DQ_WIDTH × 2 ×
AFI_RATIO
MEM_READ_DQS_
WIDTH × AFI_RATIO
AFI_RATIO
1
1
Width
Section IV. RLDRAM II Controller with UniPHY IP User Guide
Half-rate or full-rate clock supplied to
controller and system logic.
Reset output on afi_clk clock domain. For
use as asynchronous reset. This signal is
asynchronously asserted and
synchronously de-asserted.
Row address.
Bank address.
Column address strobe (CAS).
Chip select.
Row address strobe (RAS).
Write enable.
Data mask input that generates mem_dm.
Write data input that generates mem_dq.
Write data valid that generates mem_dq and
mem_dm output enables.
Read data
Doing read input. Indicates that the memory
controller is currently performing a read
operation.
Read data valid indicating valid read data on
afi_rdata, in the byte lanes and
alignments that were indicated on
afi_rdata_en.
‘1’ signals that calibration has completed
‘1’ signals that calibration has failed
External Memory Interface Handbook Volume 3
Description
6–11