IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 23

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
Generated Files
Generated Files
Table 2–4. Generated Directory Structure and Key Files—MegaWizard Plug-In Manager Synthesis Flow
December 2010 Altera Corporation
<working_dir>/
<working_dir>/
<working_dir>/<variation_name>/ <variation_name>_<stamp>.v
<working_dir>/<variation_name>/ <variation_name>_<stamp>_*.v
<working_dir>/<variation_name>/ <variation_name>_<stamp>_*.sv
<working_dir>/<variation_name>/ <variation_name>_<stamp>.sdc
<working_dir>/<variation_name>/ <variation_name>_<stamp>.ppf
<working_dir>/<variation_name>/
<working_dir>/<variation_name>/ <variation_name>_<stamp>_*.tcl
<working_dir>/<variation_name>/ <variation_name>_<stamp>_readme.txt
Note to
(1) <stamp> is a unique identifier determined by the MegaWizard Plug-in Manager at generation time.
Table
MegaWizard Plug-in Manager Flow
Directory
2–4:
f
1
For information about HardCopy issues such as vertical I/O overhang, PLLs adjacent
to I/Os, and timing closure, refer to
HardCopy III Device Handbook, Volume 1, and
HardCopy IV Device Handbook, Volume 1.
When you complete the IP generation flow, there are generated files created in your
project directory. The directory structure created varies somewhat, depending on the
tool used to parameterize and generate the IP
The PLL parameters are statically defined in the <variation_name>_parameters.tcl at
generation time. To ensure timing constraints and timing reports are correct, when
you use the GUI to make changes to the PLL component, apply those changes to the
PLL parameters in this file.
The tables in this section list the generated directory structure and key files of interest
to users, resulting from the MegaWizard Plug-in Manager flow.
Synthesis
Table 2–4
flow with the MegaWizard Plug-in Manager.
lists the generated directory structure and key files created by the synthesis
<variation_name>.qip
<variation_name>.v (for Verilog), or
<variation_name>.vhd (for VHDL)
<variation_name>_<stamp>_pin_assignments.tcl
(1)
File Name
HardCopy III Device I/O Features
(1)
(1)
(1)
(1)
(1)
(1)
Section IV. RLDRAM II Controller with UniPHY IP User Guide
HardCopy IV Device I/O Features
(1)
External Memory Interface Handbook Volume 3
QIP file which refers to all
generated files in the synthesis
fileset.
Top-level wrapper for synthesis
files.
UniPHY top-level wrapper.
UniPHY Verilog RTL files.
UniPHY SystemVerilog RTL files.
Synopsys constraints file.
Pin Planner file.
Pin constraints script to be run
after synthesis.
Other Tcl scripts.
Readme text file.
Description
in the
in the
2–13