IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 34

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–6
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
Board Skews
Skews between PCB traces can reduce timing margins.
Table 3–9
Table 3–9. Board Skews Settings
Minimum delay difference between
CK and DK
Maximum delay difference between
CK and D
Maximum delay difference between
devices
Maximum skew within QK group
Maximum skew between QK groups
Maximun skew within
address/command bus
Average delay difference between
address/command and CK
Average delay difference between
write data signals and DK
Average delay difference between
read data signals and QK
describes the board skew settings.
Parameter
The minimum delay difference between the CK signal and
any DK signal when arriving at the memory device(s). The
value is equal to the minimum delay of the CK signal minus
the maximum delay of the DK signal. The value can be
positive or negative.
The maximum delay difference between the CK signal and
any DK signal when arriving at the memory device(s). The
value is equal to the maximum delay of the CK signal minus
the minimum delay of the DK signal. The value can be
positive or negative.
The maximun delay difference of data signals between
devices. For example, in a two-device configuration there is
greater propagation delay for data signals going to and
returning from the furthest device relative to the nearest
device.
The maximum skew between the DQ signals referenced by
a common QK signal.
The maximum skew between QK signals of different data
groups.
The maximum skew between the address/command
signals.
A value equal to the average of the longest and smallest
address/command signal delay values, minus the delay of
the CK signal. The value can be positive or negative.
A value equal to the average of the longest and smallest
write data signal delay values, minus the delay of the DK
signal. Write data signals include the DQ and DM signals.
The value can be positive or negative.
A value equal to the average of the longest and smallest
read data signal delay values, minus the delay of the QK
signal. The value can be positive or negative.
Description
December 2010 Altera Corporation
Chapter 3: Parameter Settings
Board Settings